FIG. 1 is a diagram illustrating an inductor-inductor-capacitor (LLC) resonant inverter circuit consisting of conventional MOSFET switches.
In the LLC resonant inverter circuit as shown in FIG. 1, MOSFET switch M1 and MOSFET switch M2 are alternately switched to supply energy to the load. In this case, if M1 and M2 are driven at a switching frequency which is higher than a resonant frequency that is determined by an inductor L1, a capacitor C1, and a magnetizing inductance, the switches can be turned ON when the drain-source voltage of either M1 or M2 is almost zero. Such an operation is referred to as a “zero-voltage switching (ZVS)”. By performing a ZVS operation, not only can switching loss of switches be minimized, but also electromagnetic interference can be reduced.
FIG. 2 is a circuit diagram of a synchronous buck converter of a prior art.
In the synchronous buck converter that is configured as shown in FIG. 2, when M1 is ON, energy is supplied to the load via L1. Then, when MI is OFF, the inductor current free-wheels through M2, and at this time, the drain-source voltage at both ends of M2 nears zero, thus satisfying the ZVS.
FIG. 3 is an equivalent circuit diagram in the case of the ZVS performed using a conventional gate driver.
FIG. 3 shows an equivalent circuit diagram when a switch that satisfies ZVS conditions is turned ON using a conventional gate driver 10. As the ZVS condition, the drain of M1 is at the same potential as the source. In FIG. 3, the drain of M1 is set to ground level. At this time, when M2 is turned ON, M1 is also ON, thereby completing the ZVS. For M1 to be ON, a gate-source parasitic capacitor Cgs and a gate-drain parasitic capacitor Cgd have to be charged above a threshold voltage which causes the MOSFET to be ON. The power Pdriving which is provided from a power supply VDD is obtained by Equation 1 below.
                                                        Pdriving              =                            ⁢                              Qg                ·                VDD                ·                f                                                                                        =                            ⁢                                                (                                      Cgs                    +                    Cgd                                    )                                ·                                  VDD                  2                                ·                f                                                                        (        1        )            
Since Qg, which denotes charge to be supplied, is (Cgs+Cgd)*VDD, Pdriving is proportional to the total parasitic capacitance (Cg=Cgs+Cgd) of the gate, as shown in Equation 1. It is also proportional to the square of driving voltage, as well as to a switching frequency. In the case where the driving frequency is low, although gate drive loss is usually negligible compared to conduction loss caused by ON resistance Rdson of the MOSFET, the gate drive loss increases with the rise of the frequency, which means no matter how much Rdosn of the switch is improved, it is not possible to implement a system that has a good efficiency.